IRC log for #qi-hardware on 20170628

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01:08.35*** join/#qi-hardware promach__ (~promach@2001:e68:4427:c1c5:3e91:a694:8b58:1e38)
01:53.06*** join/#qi-hardware DocScrutinizer05 (~saturn@openmoko/engineers/joerg)
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10:01.15promachDocScrutinizer05: I need to find out why the book needs to use Figure b
10:03.34promachFor UART, if Tx device transmits at 9600Hz, Rx device need to sample at sampling frequency of at least twice that of 9600Hz ?
10:05.30DocScrutinizer05yes
10:05.46DocScrutinizer05more like 16*
10:07.59DocScrutinizer05the circuit in the book lacks a DC-blocker cap and 3* R for biasing input. They simplified and messed it up due to too much simplification
10:08.30DocScrutinizer052*R at least
10:11.17promachhuh ? 2*R ? where ?
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11:29.56promachfor UART Rx, what's the benefit of sampling more often?
11:43.47*** join/#qi-hardware sb0 (~lekernel@121.139.198.203.static.netvigator.com)
11:45.16DocScrutinizer05detecting edges, so you know more precisely where's *middle* of a bit time window
11:47.33DocScrutinizer05UART waits for leading edge of startbit, then samples all data bits at middle of the bit period. since the clock for the hw isn't async, it needs an as finfrained as possible oversampling to detect *leading* edge of startbit to map it to internal clock
11:47.58DocScrutinizer052*R at input to bias
11:49.11DocScrutinizer05alas that would also attenuate the input signal, or at least change input impedance, so they ommitted it
11:54.33DocScrutinizer05for an analog amp you want all transistors (except in complementary bridges, and even there depending on whether it's more of a class A or AB or class B) to draw some quiescent current
11:54.58DocScrutinizer05tying input gate to GND doesn't make sense in that circuit in your book
11:55.25DocScrutinizer05the amp is in extreme clipping situation
12:03.41DocScrutinizer05re UART I wasn't as clear as I should. The clock needs to be 8 or 16 times higher than bitrate. So the leading edge of startbit can get determined to a 1/8 or 1/16 of bit-time precision. Then (for 16 times oversampling) the hardware samples all subsequent data bits at $time_of_startbit_edge + N(bit)*16 + 8
12:04.40DocScrutinizer05the "jitter" you have is bitrate/16 then, since the clock won't phaseshift on detecting startbit leading edge
12:05.58DocScrutinizer05*if* you had a clock oscillator you could stop, and then start it on detecting leading edge of startbit, then a oscillator clock frequency of bitrate*2 would suffice
12:06.54DocScrutinizer05then you,d sample first bit on clock period#3, 2nd bit on #5, 3rd on #7 a s o
12:07.59DocScrutinizer05since you use an exernal clock, you want oversampling to approximate that ideal behavior
12:10.37DocScrutinizer05it's all about the precision of your detecting the startbit leading edge
12:10.46promachgive me a moment on UART.
12:13.15DocScrutinizer05https://en.wikipedia.org/wiki/Aliasing
12:13.58DocScrutinizer05not exactly to the point, but related
12:18.15promachDocScrutinizer05: Why (for 16 times oversampling) the hardware samples all subsequent data bits at $time_of_startbit_edge + N(bit)*16 + 8
12:18.24DocScrutinizer05your (external) clock and the serial data bitrate 'clock' interfere aka "alias" with each other, since the external clock isn't synced to the bitrate. so with a clock frequency of bitrate * 2 your databit sampling could happen *anywhere' within the bit period, from leading edge to trailing edge. With 4 times oversampling it will happen anywhere from 25% to 75% of bit period, so a lot closer to the center already
12:22.58promachWhy With 4 times oversampling it will happen anywhere from 25% to 75% of bit period ?
12:23.39DocScrutinizer05first sampling point detects startbit level. now you add 1 bitperiods and sample again. When will this sample happen? Answer: anywhere between startbit-leading-edge+0 + 1_bit_period, and startbit+startbitduration + 1_bit_period
12:24.32DocScrutinizer05Why With 4 times oversampling it will happen anywhere from 25% to 75% of bit period ? ::: because then the startbit leading edge gets detected with a precision of bitperiod/4
12:25.19DocScrutinizer05you don't know when the startbit leading edge happens since the UART only **samples** to detect the edge
12:25.41DocScrutinizer05you only know with a precision of the sample period
12:25.56DocScrutinizer05it's not edge triggered
12:29.35DocScrutinizer05it's sort of like Heissenberg
12:30.22promach<PROTECTED>
12:30.34DocScrutinizer05hmm?
12:30.59promachhow do you get 75% for 4 times oversampling ?
12:32.05DocScrutinizer050% to 25%, 25% to 50%, 50% to 75%, and 75% to 100%. So your precision is +/- 25%, aka from 25% to 75%
12:32.33promachI do not understand ?
12:32.36promachwhat about  startbit+startbitduration + 1_bit_period ?
12:32.42DocScrutinizer05and you got an 'error margin' of 25% to both leading and trailing edge
12:33.15DocScrutinizer05sorry, I give up, I'm not up to the task of explaining this
12:33.44promachnever mind. I found that to obtain Rout, Vin has to be shorted to ground
12:33.50promachwhich is Figure b
12:34.58DocScrutinizer05that's gibberish
12:37.33DocScrutinizer05I don't know who came up with this
12:38.23DocScrutinizer05it's faintly correct for *real* working circuits, but figure b is no working circuit, it's defect by design since it has no bias
12:38.43DocScrutinizer05and no DC decoupling to protect the bias
12:39.05promachFigure b is a test circuit to measure Rout
12:39.31DocScrutinizer05sorry, I got other stuff to do
12:39.54DocScrutinizer05you can't measure the Rout of a broken circuit
12:40.00DocScrutinizer05it's meaningless
12:42.11DocScrutinizer05the circuit is meant for an input voltage swing of maybe GND+0.7V to VDD-<whatever>. Outside of that voltage range the circuit doesn't work, so it's bullshit to probe for any properties of the circuit when grounding input
12:45.14DocScrutinizer05sorry I have to say that, but that except of the suggests the book is wrong regarding that. I can't rule out the rest of the book provides context that redefines the situation
12:45.25DocScrutinizer05excerpt*
12:45.40DocScrutinizer05of the book
12:45.54promachhttps://electronics.stackexchange.com/questions/242397/why-should-we-set-input-source-equal-zero-for-calculating-output-resistance-of-c
12:48.48*** join/#qi-hardware dandon (~dandon@185.16.52.158)
12:48.52DocScrutinizer05so what? doesn't apply to circuits operated outside their operational range
12:49.47DocScrutinizer05"zero" means "with respect to the allowed input voltage swing, which is +/-x Volt around zero"
12:50.29DocScrutinizer05for your circuit 0 volt isn't the middle of the allowed voltage swing, it isn't even inside allowed voltage swing at all
12:51.30DocScrutinizer05somebody ommitted bias, as I said a dozen times already
12:51.52DocScrutinizer05that circuit is broken from oversimplification
12:52.32DocScrutinizer05depending on particular type of MOSFET used in input stage
12:52.57DocScrutinizer05the usual mosfet will close completely when gate is on source level
12:53.24DocScrutinizer05so that transistor isn't operating in its linear range which is a BAD THING for a linear amp
12:54.46DocScrutinizer05not in linear rnage means the transistor can't close even more when you apply a negative voltage with respect to GND to the input. Usually that is called CLIPPING
12:55.27DocScrutinizer05clipping is something you need to avoid by all means for a linear amp
12:56.20promachDocScrutinizer05: that test circuit is for small-signal analysis of Rout
12:57.12DocScrutinizer05WTF, you build a circuit that is made to test some property of that circuit? what's its true useage
12:57.42DocScrutinizer05small signal HAHA. There is no signal small enough to bring that test circuit in b) out of clipping
12:57.45DocScrutinizer05so forget it
12:58.29DocScrutinizer05tis IS NO amp
12:58.58DocScrutinizer05it starts to become an amp when you apply at least 0.7V bias with respect to GND
12:59.03promachhttps://inst.eecs.berkeley.edu/~ee105/fa14/lectures/Lecture13-Small%20Signal%20Model-MOSFET.pdf
12:59.11DocScrutinizer05MEH!
12:59.17DocScrutinizer05go take it elsewhere
12:59.21promachthis is small-signal analysis, not DC analysis
12:59.30DocScrutinizer05bullshit
13:00.07DocScrutinizer05google clipping
13:00.17DocScrutinizer05then google DC-bias maybe
13:01.32DocScrutinizer05my ass
13:02.33DocScrutinizer05what you get in fig b) is Rout of an amp **IN CLIPPING MODE**. Everybody can tell you an amp in clipping doesn'T work as amp anymore
13:03.22DocScrutinizer05it's saturated, clipping, outside of specs, not functional
13:04.02DocScrutinizer05not my fault you forgot DC-bias of input gate and DC-blocker capacitor
13:05.03DocScrutinizer05go test your thing in a simulator, you will notice it has a gain of -infinite
13:05.54DocScrutinizer05unless you apply a bia of at least 0.7 V (or whatever t´is that particular MOSFETs gate voltage where it starts to open D-S channel)
13:07.05promachI know you are concerned about DC analysis, but simulator also has AC analysis, right ?
13:07.07DocScrutinizer05ZERO means AC-zero, NOT DC-zero
13:07.16DocScrutinizer05NOOOO!
13:07.45promachit definitely has, otherwise, we will not have gain-phase plot
13:07.58promachbode plot
13:08.01DocScrutinizer05what the fuck is so hard to understand in "fig b) doesn't show an amp"?
13:08.20promachI understand that  "fig b) doesn't show an amp"?
13:08.27DocScrutinizer05no fucking DC-analysis, ITS BROKEN BY DESIGN
13:08.38promachit is not meant for DC analysis
13:08.57DocScrutinizer05so why do you drive it DC then??????
13:09.22DocScrutinizer05tying gate to GND **IS DC**
13:09.26promachVin is not driven by DC anymore
13:09.33promachafter shorting to GND
13:09.46DocScrutinizer05apply two resistors for bias, and a DC-blocker capacitor and you are fine
13:09.58DocScrutinizer05headdesks
13:09.59promachin AC analysis, DC bias is deemed GND
13:10.04DocScrutinizer05please take it elsewhere
13:10.59DocScrutinizer05your refusal to accept the simple fact that this circuit is broken by design starts to annoy
13:11.30promachit is broken in DC analysis
13:11.34promachnot in AC analysis
13:12.20DocScrutinizer05initally you seem to have spotted the problem yourself when you asked why the feedback isn't working. It's not working BECAUSE the circuit is operated outside specs since it's missing bias and DC-blocking on input
13:12.40DocScrutinizer05fuck, you really are annoying
13:13.29DocScrutinizer05its broken. as linear amp. period.
13:13.38DocScrutinizer05no matter which analysis you run against it
13:13.56promachI just understand about AC analysis just now
13:15.17DocScrutinizer05do you understand about electronics too?
13:15.32DocScrutinizer05or _just_ about analysis
13:17.31DocScrutinizer05when this is about education at university then I have little hope for good circuits in the future
13:19.27DocScrutinizer05>>in AC analysis, DC bias is deemed GND<< yes, OUTSIDE your blackbox DUT
13:19.44DocScrutinizer05your blackbox however is missing INTERNAL bias
13:21.01DocScrutinizer05what makes you think your circuit can get away without the DC-blocker capacitor and internal input bias EVERY OTHER circuit has?
13:21.54DocScrutinizer05s/circuit/non-differential amp/
13:21.56qi-botDocScrutinizer05 meant: "what makes you think your non-differential amp can get away without the DC-blocker capacitor and internal input bias EVERY OTHER non-differential amp has?"
13:22.09DocScrutinizer05s/circuit/non-differential amp/g
13:22.20kyakDocScrutinizer05: fear not - younger generations are always better than older despite older thinking otherwise :)
13:22.32DocScrutinizer05I see
13:23.05DocScrutinizer05google "operation point"
13:23.39DocScrutinizer05secod hit is "bias"
13:24.17DocScrutinizer05https://en.wikipedia.org/wiki/Operating_point  https://en.wikipedia.org/wiki/Biasing
13:25.08DocScrutinizer05https://en.wikipedia.org/wiki/Biasing#Importance_in_linear_circuits
13:26.56DocScrutinizer05>>For low distortion, the transistor must be biased so the output signal swing does not drive the transistor into a region of extremely nonlinear operation.<< tying gate to source puts the mosfet into a mode as extremely nonlinear as it gets: it's closed
13:27.54DocScrutinizer05>>the MOSFET must stay in the active mode (or saturation mode), and avoid cut-off or ohmic operation (or triode mode).<<
13:28.33DocScrutinizer05ETX, bye
13:44.51DocScrutinizer05listen buddy, when you're doing AC-analysis the you tie input to GND via a DC-blocker capacitor. You MUST NOT apply DC-bias in the form of tying input to GND with a wire
13:45.18DocScrutinizer05however you're doing exactly that and then you call it AC-analysis
13:47.10DocScrutinizer05get your educational books fixed!
13:48.34DocScrutinizer05when you actually do tie input to GND via a DC-blocker capacitor, you will notice your circuit is junk since it has no input bias circuit defining the operation point of the input stage transistor. The gate is floating
13:49.09DocScrutinizer05operating point*
14:00.49DocScrutinizer05your initial question was extremely cute. You found that Rout should differ in *normal operation* from what been calculated by the small signal AC analysis method in https://electronics.stackexchange.com/questions/242397/why-should-we-set-input-source-equal-zero-for-calculating-output-resistance-of-c, due to feedback not working when circuit is not at operation point. Now you just need to stand your thesis and argue why that's
14:00.50DocScrutinizer05probably a bad thing
14:02.07DocScrutinizer05sure you can test Rout at clipping mode, the question is if that's really what you want to know
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14:19.53enycoo fun
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