| 01:40.28 | *** join/#qi-hardware atommann (~atommann@58.251.2.94) |
| 01:41.43 | arossdotme | got any photo of china factorys that could be used in something say like a info graphic? from a real life photo to a simple,basic - ie: 2 colour outline,silo-wet(cant spell the word i mean) - icon representation of a factory? |
| 01:44.06 | arossdotme | or pictures along the lines of portable computer product life cycle, designed/plotted (planned) obsolescence that you have came across? |
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| 14:48.30 | kristianpaul | moin |
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| 19:04.17 | whitequark | <furan>Ihttps://github.com/cseed/arachne-pnr Arachne-pnr implements the place and route step of the hardware compilation process for FPGAs. It accepts as input a technology-mapped netlist in BLIF format, as output by the Yosys [0] synthesis suite for example. It currently targets the Lattice Semiconductor iCE40LP/HX1K FPGA [1]. |
| 19:05.42 | kristianpaul | oh |
| 19:05.55 | kristianpaul | wait wait, so this is another HDL ? |
| 19:06.00 | kristianpaul | clicks |
| 19:06.43 | kristianpaul | is that private whitequark ? |
| 19:07.00 | kristianpaul | nm |
| 19:07.10 | whitequark | no, not a HDL |
| 19:07.13 | whitequark | this is a PAR for lattice |
| 19:07.33 | kristianpaul | but yosys uses abc i think for PAR no? |
| 19:08.41 | whitequark | abc is for ASIC |
| 19:08.50 | whitequark | there was no OSS PAR for FPGAs so far |
| 19:08.55 | whitequark | (fpgatools don't count) |
| 19:09.12 | kristianpaul | sure not fpgatools is just foorplan |
| 19:11.18 | kristianpaul | hmm i tought yosys was doing PAR for its ice40 lib.. |
| 19:11.36 | kristianpaul | still too early to speak, he commits everday.. |
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| 19:34.54 | whitequark | well, it already works to a degree |
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