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| 13:37.04 | valhalla | I've flashed the latest uboot (2012-07-11) on the nanonote and now it isn't booting from SD anymore (I press M+power it cycles inside uboot until I release M, and then starts from the nand) |
| 13:42.33 | xiangfu | valhalla, sorry about the bug, the code is same, after we update the gcc/uclibc, it woldn't boot from sd anymore |
| 13:43.07 | kristianpaul | :o |
| 13:43.14 | xiangfu | valhalla, please revert back to : http://downloads.qi-hardware.com/software/images/NanoNote/Ben/2011-11-13/openwrt-xburst-qi_lb60-u-boot.bin |
| 13:43.37 | xiangfu | valhalla, I will try to fix that bug next few days. (I am slow) |
| 13:46.33 | xiangfu | kristianpaul, Hi |
| 13:46.48 | xiangfu | kristianpaul, I have one fpga question. |
| 13:47.33 | kristianpaul | oh sure |
| 13:47.38 | kristianpaul | Hi ! |
| 13:48.09 | valhalla | xiangfu: ok, so it is a known problem, thanks |
| 13:48.09 | xiangfu | kristianpaul, here is a simple verlog code. |
| 13:50.10 | xiangfu | kristianpaul, if I don't connect any oscillator, the 'y'(which I connect a led) will flash. where is the clock from? |
| 13:50.48 | kristianpaul | i think i missed your pastebin.. |
| 13:51.26 | kristianpaul | you dont need an oscillator all times, it varies from what you want to synthesize |
| 13:52.54 | xiangfu | kristianpaul, here: http://pastebin.com/kLTn9JS2 |
| 13:54.17 | kristianpaul | and the .ucf? |
| 13:54.47 | xiangfu | kristianpaul, http://pastebin.com/bA6sxiKj |
| 13:55.31 | xiangfu | kristianpaul, there is nothing connect to P55. |
| 13:56.09 | kristianpaul | okay but is unconeected? |
| 13:56.15 | kristianpaul | not even grounded? |
| 13:56.39 | xiangfu | no ground. nothing. |
| 13:56.46 | kristianpaul | wich would made me think thats where you clock came from :) |
| 13:56.56 | kristianpaul | ah |
| 13:57.10 | xiangfu | that is my question. I use jtag load the bitstream to chip. |
| 13:58.31 | kristianpaul | i *think* your "clock" just came from the static, |
| 13:59.19 | kristianpaul | if you have a scope around you could try to see the LED input from fpga |
| 13:59.31 | kristianpaul | i bet is not that stable clock at all |
| 14:00.50 | kristianpaul | jtag have its own clock, not to be related with any other clock source used on your verilog project |
| 14:00.54 | kristianpaul | xiangfu: u there? |
| 14:00.58 | xiangfu | yes |
| 14:01.30 | kristianpaul | why you not try to ground that P50 |
| 14:01.39 | xiangfu | you mean P55? |
| 14:01.52 | kristianpaul | ah yes sorry |
| 14:01.58 | xiangfu | kristianpaul, here is my board: http://en.qi-hardware.com/wiki/Mini-slx9 |
| 14:02.20 | kristianpaul | from the verilog it self or externally |
| 14:02.20 | xiangfu | kristianpaul, all pins are not ground . I only connect the pins I am using. |
| 14:02.42 | kristianpaul | well, in your UCF file you claim that will use that P55 |
| 14:02.51 | kristianpaul | you dint.. but you either ground it.. |
| 14:03.07 | kristianpaul | so this could lead to unknow behavior i think |
| 14:03.35 | kristianpaul | ah nice board ! |
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| 14:04.13 | kristianpaul | xiangfu: what i said answer your question? |
| 14:05.01 | xiangfu | (lead to unknow behavior i think). ok. |
| 14:05.39 | kristianpaul | i'm not 100% certain |
| 14:05.55 | kristianpaul | but just what i learn from milkymist, ie this https://github.com/milkymist/milkymist/blob/master/boards/milkymist-one/rtl/system.v#L1103 |
| 14:06.23 | xiangfu | ok. I have 40M,20M,8M,6M,2M oscillator |
| 14:06.28 | kristianpaul | made me think if not using it you should ground it "assign mc_clk = 1'b0;" |
| 14:06.34 | xiangfu | I try to connect 40M/20M to P55. |
| 14:06.39 | kristianpaul | in your case externally |
| 14:07.39 | kristianpaul | what happen when you connect it? |
| 14:08.00 | xiangfu | but the mc_clk is output. not like my P55(input) |
| 14:08.17 | kristianpaul | ahh true |
| 14:08.35 | xiangfu | kristianpaul, nothing happen. I keep get 0 from 'x' |
| 14:08.52 | xiangfu | I also not sure if my little oscillator board is working. |
| 14:09.06 | xiangfu | I just connect 3.3v and GND to the osc. and connect one wire to P55. |
| 14:09.18 | kristianpaul | you have scope? |
| 14:10.08 | xiangfu | from the datasheet. it says the userclk must be short then 0.8cm (Stubs, if necessary, must be shorter than 8 mm (0.3 inches).) |
| 14:10.46 | kristianpaul | hmm |
| 14:10.53 | xiangfu | kristianpaul, I have a usb scope. dso2090. but after update my system the 'openhantek' command not working any more. |
| 14:11.00 | wpwrak | your little board probably violates a 1000 design recommendations already. what's one more ? ;-)) |
| 14:11.17 | xiangfu | wpwrak, :-) |
| 14:11.22 | kristianpaul | xD |
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| 14:11.49 | wpwrak | just try to run things at slow clocks and slow I/O (QUIETIO sounds good), then you should be able to get away with most things. |
| 14:14.08 | xiangfu | wpwrak, yes. I have 40M/20M osc on my desk. the 8M/6M/2M osc is one the way to my desk. :) |
| 14:15.09 | xiangfu | hope the 2M is slow enough. |
| 14:16.21 | xiangfu | the hdl code is interesting. is not running line by line. once power on. all lines code are running. :) |
| 14:16.50 | kristianpaul | yup |
| 14:17.09 | kristianpaul | as it is sinthesized |
| 14:17.22 | xiangfu | wpwrak, I read the QUIETIO is better for LED. |
| 14:17.47 | xiangfu | in fact I am not question understand. when should i use QUIETIO/SLOW/FAST |
| 14:18.14 | xiangfu | kristianpaul, wpwrak : after I remove 'clk/P55' the led still flashing. the code is like: http://pastebin.com/rYb33fVS |
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| 14:19.24 | kristianpaul | how you connected a and b? |
| 14:20.37 | xiangfu | to 3.3v |
| 14:21.34 | kristianpaul | btw your counter missed a reset.. guess not matter much here but just to get used to use it :) |
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| 14:23.59 | kristianpaul | but is flashing under the espected freq? |
| 14:24.09 | kristianpaul | if you ground 1 or b, it should stop |
| 14:24.13 | kristianpaul | s/1/a |
| 14:24.13 | qi-bot | kristianpaul meant: "if you ground a or b, it should stop" |
| 14:25.35 | xiangfu | it's flashing at expected freq. |
| 14:25.51 | xiangfu | if I ground b or a to GND, it will stop. |
| 14:26.03 | xiangfu | all works like there is a clock somewhere. |
| 14:28.34 | kristianpaul | the counter :-) |
| 14:32.32 | kristianpaul | thats your clock source |
| 14:34.02 | xiangfu | what you mean? |
| 14:34.47 | kristianpaul | your hdl code describe something that looks like a counter |
| 14:37.55 | kristianpaul | you have the build log at hand? |
| 14:38.33 | xiangfu | kristianpaul, I can rebuild it now. wait |
| 14:42.49 | xiangfu | kristianpaul, here is the full log: http://pastebin.com/6aGMku8k |
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| 14:45.39 | kristianpaul | ah look line 111 |
| 14:45.54 | kristianpaul | that is a loop aka your clock source :-) |
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| 14:52.12 | xiangfu | still don't understand :( |
| 14:53.07 | kristianpaul | you could make a clock using combinational logic |
| 14:53.54 | kristianpaul | thats a circuit input is fed by it own output |
| 14:54.04 | kristianpaul | so is a loop |
| 14:54.09 | xiangfu | ok |
| 14:54.38 | xiangfu | kristianpaul, thanks. I got it. |
| 14:54.43 | kristianpaul | sure? .. |
| 14:55.00 | kristianpaul | i still thinkking.. well i dont know how xst sinthesized it.. |
| 14:55.26 | xiangfu | I got some idea. not very clear. my goal is connect the external osc. this is not very important for now. :) |
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| 14:55.40 | kristianpaul | ah ok |
| 14:55.59 | kristianpaul | you could even made an osc of the fpga, using a couple not gates in a loop :) |
| 14:56.22 | xiangfu | kristianpaul, is there some code? :) |
| 14:57.05 | kristianpaul | second |
| 14:57.17 | kristianpaul | oops, better minute i'm looking |
| 15:13.44 | kristianpaul | damn, so far i just found this ilustration http://goo.gl/oibwQ |
| 15:15.46 | xiangfu | sure I just take a look. and learn |
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| 15:28.17 | Fallenou | xiangfu: hey :) experimenting some fpga design ? :) |
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| 15:46.15 | LunaVorax | hi |
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| 20:14.00 | Jay7 | http://youtu.be/ikD_3Vemkf0 |
| 20:14.10 | Jay7 | 3d tracking interface |
| 20:14.29 | Jay7 | even so: http://makeprojects.com/Project/A-Touchless-3D-Tracking-Interface/2233/1#.UCgOnztlyXI |
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