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| 12:41.13 | ja2 | Hi, I just ran openocd 0.4.0 flash write_image but get error writing to flash at address 0x60000000 at offset 0x000c0000 (-902) Any ideas on how to solve this? I have work-area-phys 0x80014000 size 0x1000 and no backup. It is an EP9307 target using a olimex jtag tiny. |
| 12:46.20 | Weaselweb | ja2: rerun openocd with increased loglevel (-d) |
| 12:47.56 | ja2 | core.c:76 flash_driver_write(): error writing to flash at address 0x60000000 at offset 0x000c0000 (-902) |
| 12:47.56 | ja2 | So I look there. |
| 12:49.45 | Weaselweb | no other errors? |
| 12:52.41 | Weaselweb | what kind of flash do you use? an intel one? |
| 12:53.47 | ja2 | No errors I can see. MT28F640J3 flash. |
| 12:54.03 | ja2 | Dont know if it intel how manuf. those. |
| 12:54.17 | ja2 | +is |
| 12:56.02 | Weaselweb | i found only 3 positions where this error gets issued without error message, all are in functions for intel command NOR flashes |
| 12:58.44 | ja2 | I flashed a new u-boot just previously. this new u-boot change the (external) RAM from 32-bit to 16-bit. Thereby losing half of my RAM, but that is what I want. The work-area openocd uses is a MAC FIFO buffer in the EP9307 chip. |
| 12:58.53 | ja2 | I didnt think it would be affected. |
| 12:59.38 | Weaselweb | ja2: which actual command did you use? |
| 12:59.51 | ja2 | Well, this warning (-902) was issued in the first u-boot flash too. But power toggle/restart openocd solved that. |
| 13:00.19 | ja2 | flash write_image /tmp/uImage.bin 0x600c0000 |
| 13:01.19 | Weaselweb | try flash write_image erase /tmp/uImage.bin 0x600c0000 |
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| 13:02.39 | ja2 | I did a soft_reset_halt. That solved the problem. |
| 13:02.57 | ja2 | By that I get control over the chip before u-boot change the ram width, |
| 13:03.30 | Weaselweb | doesn't this ARM have internal SRAM which you can use a workspace? |
| 13:03.30 | ja2 | 6 sections was flashed, but then -902 again. |
| 13:03.54 | ja2 | No, it is just 0x10ff bytes of fifo that I can use. |
| 13:04.18 | Weaselweb | don't you need to setup PLL and stuff first? |
| 13:05.08 | ja2 | Doesnt seem to need to set up PLL. Maybe I run the jtag slow enough to work with the 14 Mhz crystal. |
| 13:06.54 | ja2 | Anyway, the flash write_image should work without erase. Just filling in 0's where there was 1's previously. |
| 13:08.19 | Weaselweb | ja2: i don't know if this also matches to EP93, but on AT91 I can run 1/6 of my slowclock which is 32kHz |
| 13:10.08 | ja2 | I never found the exact info on what jtag speed to use for this chip. My cfg files worked well with openocd 0.2.0, so I should fall back and test there, so nothing bad have happened with the hw. Have to change computer/login to do that though... |
| 13:14.04 | Weaselweb | you can do a svn checkout on version 0.2.0 and recompile |
| 13:14.22 | ja2 | Got a new error running the jtag at 1 khz; |
| 13:14.24 | ja2 | Error: 508 152841 arm7_9_common.c:718 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: 5 |
| 13:14.32 | ja2 | Error: 509 152841 cfi.c:1141 cfi_intel_write_block(): Unable to write block write code to target |
| 13:14.38 | ja2 | *** glibc detected *** openocd: free(): invalid pointer: 0x00525819 *** |
| 13:14.43 | ja2 | +dump |
| 13:16.02 | ja2 | Well, maybe not so strange... |
| 13:17.51 | Weaselweb | ja2: the 1st 2 lines sound like real error messages, but the last one seem to be wrong error handling |
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