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| 18:14.34 | prpplague | drath: ping |
| 18:24.59 | drath | prpplague: pong |
| 18:25.09 | prpplague | drath: oh good you are there |
| 18:25.25 | prpplague | drath: question, whats the syntax for configuring nand flash in the .cfg file? |
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| 18:39.14 | drath | prpplague: "nand device <driver> [driver options]" |
| 18:39.31 | prpplague | drath: yea, just found it in the code |
| 18:39.42 | prpplague | drath: so for example |
| 18:39.48 | prpplague | drath: the lpc3180 would be |
| 18:39.58 | prpplague | drath: nand device lpc3180 |
| 18:40.15 | drath | for the lpc3180 it's: |
| 18:40.17 | drath | nand device lpc3180 <target#> <oscillator_frequency> |
| 18:41.02 | prpplague | ahh gotcha |
| 18:41.04 | drath | most NAND's are going to have a <target#> |
| 18:41.22 | drath | because the NAND is always connected to a target |
| 18:41.49 | drath | but I thought about a generic boundary-scan NAND driver, in which case you'd have a <jtag-index> instead |
| 18:42.25 | drath | not sure about the S3C24xx, but for the LPC3180 you have to specify several timing parameters as well |
| 18:42.56 | drath | the lpc3180 uses the <oscillator_frequency> to calculate the current clock configuration after reading some registers |
| 18:44.18 | prpplague | drath: yea there are a few setups for the s3c24xx, but i'm not sure i understand about the "target" |
| 18:45.35 | drath | you mean the <target#>? |
| 18:46.04 | prpplague | yea |
| 18:46.40 | drath | the OpenOCD supports multiple, daisy chained targets |
| 18:46.47 | drath | so you could have several jtag_device entries |
| 18:46.52 | drath | and also several target xxxx entries |
| 18:47.16 | prpplague | drath: ahh ok, so the target is the device that the specified nand flash is connected to |
| 18:47.19 | drath | the NAND needs to know which target number it is connected to, starting with "0" for the first |
| 18:48.08 | prpplague | drath: ahh ok so for my case the it will be 0 |
| 18:48.10 | drath | i should get a AT91SAM9260 board within a few days, that'll give me the chance to implement NAND support for another device |
| 18:48.18 | drath | prpplague: yeah |
| 18:48.36 | prpplague | drath: yea i copied the lpc3180 code and have started hacking it up |
| 18:50.26 | drath | which s3c24xx are you working with? |
| 18:50.37 | drath | they've got different NAND controllers iirc, right? |
| 18:52.15 | prpplague | drath: its my understanding that the controllers on the s3c2410 and s3c2440 are the same |
| 18:53.34 | prpplague | drath: yea a quick check looks to be the same |
| 18:54.14 | drath | prpplague: ok, but 2442 for example seems to be different |
| 18:54.41 | drath | prpplague: it supports 2kb pages whereas the 2410 supports only 512b pages |
| 18:56.15 | prpplague | drath: yea thats a limitation of the 2410 configuration |
| 18:56.54 | prpplague | drath: the 2442 and 2440 are the same core , with the 2442 having some additional features available such as ram and nand flash on the same silicon |
| 18:57.06 | prpplague | drath: so if anything, the 2442 and 2440 would be identical |
| 18:57.26 | prpplague | drath: all the address space is the same from what i'm seeing |
| 19:00.21 | prpplague | drath: thanks for the info |
| 19:00.23 | prpplague | bbiab |
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| 20:29.50 | prpplague | drath: greetings |
| 20:30.52 | prpplague | drath: probing nand flash seems to be working |
| 20:31.04 | prpplague | drath: you gonna want patches submitted for these? |
| 20:31.37 | drath | prpplague: yeah, of course |
| 20:32.11 | prpplague | drath: i've just about given up on submitting patches these days, so i just wanted to make sure before i wasted my time, hehe |
| 20:35.00 | prpplague | drath: we submited a 208 patches in the last 6 months, only 3 were accepted, and around 100 really haven't even been looked at by the maintainers |
| 20:37.23 | drath | prpplague: least i'll do is check them in for others to look at |
| 20:37.40 | drath | prpplague: then, when i start working on the sam9 nand, i'll look at them again to see how the nand concept fits together |
| 20:37.41 | prpplague | drath: thanks |
| 20:37.53 | prpplague | drath: so far it looks good |
| 20:38.00 | prpplague | drath: i like the feel of it |
| 20:43.52 | prpplague | drath: hey, quick question |
| 20:44.09 | prpplague | drath: the s3c24xx use a seperate flag to control the chip select |
| 20:44.23 | prpplague | drath: i'm not seeing any routines setup for that in the lpc3180 |
| 20:51.05 | prpplague | hmm |
| 20:51.15 | prpplague | drath: another problem |
| 20:51.37 | prpplague | drath: the s3c2440 nand flash controller does 32bit data read/writes |
| 20:59.01 | drath | prpplague: the lpc3180 is rather complicated |
| 20:59.08 | drath | prpplague: you can't access the NAND bus on your own |
| 21:00.22 | prpplague | drath: i wonder what the cortex nand flash controler is like |
| 21:01.15 | prpplague | drath: i'm afraid i'm going to need to add a x32 buswidth |
| 21:01.21 | prpplague | drath: to the main nand.c code |
| 21:01.39 | prpplague | drath: because the nand controller doesn't really perform in the same manner |
| 21:02.59 | drath | hmm, the nand bus width refers to the nand chip itself, iirc |
| 21:03.13 | drath | and i don't think i've seen 32-bit NAND chips? |
| 21:04.28 | prpplague | drath: correct |
| 21:04.48 | prpplague | drath: however the nand controller itself is geared for 32bit read/writes |
| 21:05.27 | prpplague | drath: i.e. one read of the 32bit data register is the same as calling the 8bit read 4 times |
| 21:05.42 | prpplague | drath: for instance on the vendor id |
| 21:06.18 | drath | ah, yeah, but that's not what x8/x16 buswidth means |
| 21:06.29 | prpplague | drath: if you do the vendor id command and do a single read of the 32bit register you get something like 0x00003520 |
| 21:06.40 | prpplague | drath: yea i know |
| 21:07.04 | prpplague | drath: i was trying to think of the best way to handle it |
| 21:07.30 | drath | heh, it's been 6 months since i last looked at that code |
| 21:07.31 | prpplague | drath: since even though it is an 8-bit buswidth, all of that is actually hidden behind the controller |
| 21:07.33 | drath | let me check some things |
| 21:07.41 | prpplague | drath: np |
| 21:14.09 | drath | according to the 2442 manual you should be able to just do multiple bus-width accesses |
| 21:14.20 | drath | and each should return consecutive data |
| 21:14.37 | drath | only if you read multiples of the bus-width you get multiple accesses |
| 21:16.22 | prpplague | drath: hmm, that doesn't seem to be the case |
| 21:17.43 | prpplague | drath: ahh, indeed if you do a 8 bit read you get 8 bit data |
| 21:17.44 | prpplague | lovely |
| 21:19.19 | prpplague | drath: kind of a waste, but oh well |
| 21:19.53 | prpplague | "NAND flash device 'NAND 32MiB 1,8V 8-bit' found" |
| 21:20.00 | prpplague | lovely |
| 21:20.11 | drath | the write|read_page functions can be implemented for accelerated operation |
| 21:20.21 | drath | iirc |
| 21:20.30 | prpplague | > nand info 0 |
| 21:20.30 | prpplague | #0: NAND 32MiB 1,8V 8-bit (ST Micro) pagesize: 512, buswidth: 8, erasesize: 16384 |
| 21:20.30 | prpplague | #-1: 0x646e616e (0x819ddkB) erase state unknown (block condition unknown) |
| 21:20.37 | drath | i'll have to go through all this again, but not at 11:20pm ;) |
| 21:20.44 | prpplague | drath: hehe, np |
| 21:20.49 | prpplague | drath: thanks for the info |
| 21:21.01 | drath | the lpc3180 does pretty much everything on its own |
| 21:21.02 | prpplague | drath: should have it working pretty well by tomorrow |
| 21:21.12 | drath | especially in MLC mode |
| 21:21.20 | prpplague | drath: i'll generate a patch and send your way to have a look at |
| 21:21.21 | drath | the two modes are basically two different controllers |
| 21:21.27 | drath | great, thanks |
| 21:21.34 | prpplague | drath: my repo is of the svn from a couple weeks back |
| 21:21.48 | drath | that code isn't likely to change |
| 21:22.02 | drath | i'm off for today, bye |
| 21:22.34 | prpplague | drath: later |
| 21:45.15 | prpplague | drath: dump works |