| 00:41.30 | *** join/#openjtag prpplague (~billybob@72.22.133.55) |
| 08:47.43 | *** join/#openjtag ka6sox (~ka6sox@adsl-66-159-198-116.dslextreme.com) |
| 11:49.13 | *** join/#openjtag [g2] (~g2@g2.nslu2-linux) |
| 19:16.29 | *** join/#openjtag ep1220 (~ep1220@gate.epatec.at) |
| 19:17.13 | ep1220 | [g2] The firmware is not in a file, either in EEPROM |
| 19:17.25 | ep1220 | or compiled into the driver or application |
| 19:17.46 | [g2] | on the USB2 I think it's downloaded |
| 19:18.04 | ep1220 | But it is always possible to download a new firmware |
| 19:18.05 | [g2] | in the USB-JTAG I think it's in an eeprom on onboard |
| 19:18.15 | ep1220 | even if it booted out of EEPROM |
| 19:18.15 | [g2] | iirc eeprom |
| 19:20.38 | ep1220 | so I think it is possible to write a new firmware |
| 19:20.56 | ep1220 | I will get a Spartan3 board + USB in the next days |
| 19:20.57 | [g2] | possibly |
| 19:21.25 | ep1220 | Will then verify this |
| 19:21.36 | [g2] | are you getting a cable too ? |
| 19:21.45 | ep1220 | unfortunately not |
| 19:21.56 | [g2] | ok |
| 19:22.48 | ep1220 | So YOu have such a cable ? |
| 19:24.03 | [g2] | I don't but I was going to offer to get you one |
| 19:24.23 | [g2] | having the S3 and usb shows much more initiative |
| 19:24.38 | [g2] | and I don't want to distract you from the real task |
| 19:25.25 | ep1220 | To some degree I am not sure I want to spend time on the low-cost solution |
| 19:26.19 | ep1220 | Though it would be available sooner. |
| 19:26.59 | ep1220 | Which CPU do You want to debug ? |
| 19:27.29 | [g2] | IXP4xx Xscale ARM |
| 19:28.19 | [g2] | I don't have JTAG now and could use it for some debugging |
| 19:28.20 | ep1220 | See, Did some simulations. on the JTAG cable |
| 19:28.22 | ep1220 | I could get approx. 100KBytes/s download on XScale |
| 19:29.02 | [g2] | downloader are really a big issue right now |
| 19:29.33 | [g2] | the bootloader is running so I download to jffs2 @ 100Mhz via ethernet and reflash in seconds from Linux |
| 19:30.06 | [g2] | however, for other boards and sucking stuff out of flash that be really sweet |
| 19:30.59 | ep1220 | Upload maybe a bit slower (due to the way XSCALE syncs to JTAG) |
| 19:31.59 | ep1220 | I have evaluated another 8051. It would be 4times faster. |
| 19:32.20 | ep1220 | But require a PCB an a commitment to say 100 boards |
| 19:32.42 | ep1220 | So I am not sure if there would enough takers ... |
| 19:33.05 | ep1220 | Then there is Spartan. Still faster, but a lot more work :-) |
| 19:34.33 | [g2] | ep1220, couple questions |
| 19:34.46 | ep1220 | go on |
| 19:35.08 | [g2] | what do you think the PCB would cost for 100 units ? |
| 19:35.22 | [g2] | and could it also do JTAG |
| 19:35.31 | [g2] | JTAG debugging |
| 19:37.21 | ep1220 | I have only quote for main parts so far. 50-80EUR (not sure about setup cost) |
| 19:37.40 | ep1220 | Yes primarily debugging. |
| 19:38.05 | ep1220 | actually and JTAG action You want |
| 19:38.26 | [g2] | ok so .5-.8 EUR per board |
| 19:38.50 | ep1220 | i ment per board, incl. parts and manufacturing |
| 19:39.13 | [g2] | that's even better :) |
| 19:39.30 | [g2] | so that's like $180US for a run of 100 ? |
| 19:40.28 | ep1220 | 80EUR is approx. 110$ |
| 19:41.20 | [g2] | what do you want to do with the design and source code ? Is GPL ok ? |
| 19:42.12 | ep1220 | For debugging software, for sure. |
| 19:42.22 | ep1220 | For firmware not so sure. |
| 19:42.39 | ep1220 | Some processors i am interested in JTag info is under NDA |
| 19:42.48 | ep1220 | So GPL would be a problem here |
| 19:43.15 | [g2] | you wouldn't have to release the sw for that processor |
| 19:43.32 | [g2] | just release the sw for the IXP/Xscale |
| 19:43.58 | [g2] | does that make sense ? |
| 19:44.33 | ep1220 | must think about it. |
| 19:44.41 | [g2] | Wonderful. |
| 19:44.53 | ep1220 | In my plans BSD like license might also be possible. |
| 19:44.54 | [g2] | Thanks so much for your time and help |
| 19:45.23 | [g2] | BSD style license would likely work |
| 19:47.04 | ep1220 | on the Xilinx S3: are you an expert/advanced user/beginner ? |
| 19:47.20 | [g2] | beginner |
| 19:47.47 | [g2] | I'm an embedded firmware guy and I've worked right next to a bunch of high-end FPGA guys |
| 19:48.16 | [g2] | So I'm familar with all the constraints and capabilities, but not from an actual make happen perspective |
| 19:48.47 | [g2] | I have a decent understanding of floor-planning and routing constraints |
| 19:48.50 | ep1220 | the point: Using S3 + 68013 would add 20EUR parts cost - not so much, rigth (?) |
| 19:49.16 | [g2] | not to me. |
| 19:49.51 | ep1220 | But i have a hard time estimating development time |
| 19:50.25 | [g2] | well for the guys I know it'd be in the weeks range but they are experts |
| 19:50.43 | [g2] | I've been toying with actually contracting with them to just do it |
| 19:51.34 | ep1220 | Did You ask them for a price ? |
| 19:52.01 | [g2] | not yet. I've been asking to get it for free first :) |
| 19:52.25 | ep1220 | that price would be hard to beat ;-) |
| 19:52.44 | [g2] | are you an FPGA guy ? |
| 19:53.38 | ep1220 | I worked with the first Xilinx available, arond '86/87, I believe. |
| 19:53.48 | ep1220 | Since then I only did smaller CPLDs. |
| 19:54.07 | [g2] | so you are very well equiped for this taskk |
| 19:54.10 | ep1220 | Back than I had to manualy route/place 40% of the design |
| 19:54.19 | ep1220 | But then all CLBs were used :-) |
| 19:55.20 | [g2] | on the last place where the hw guys were doing FGPA we had 1.5M parts... Routing on expensive PC was talking 16-20 hours :) |
| 19:56.15 | ep1220 | I was 2weeks on that job (on a 286; 800x600VGA) |
| 19:56.28 | [g2] | :) |
| 19:56.50 | [g2] | it's a great industry if you like change |
| 19:56.56 | ep1220 | Likely the Auto Routers have improved since then. |
| 19:58.05 | [g2] | I've go to write something up. I'll be back later tonight... Thanks for chatting ! |
| 19:58.36 | ep1220 | Thank you too, I will be back tomorrow. |
| 20:04.27 | *** part/#openjtag ep1220 (~ep1220@gate.epatec.at) |