IRC log for #maemo-ssu on 20160415

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17:30.48freemangordonsailus: " 40:        599      INTC  24 Edge      480bd400.mmu, OMAP3 ISP" :)
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17:49.57freemangordonPali: ^^^ we got ISP interrupts, still no image, but at least there are signs of life
17:50.08Palinice!!!!
17:50.40freemangordonPali: to achieve that, I remove video-bus-switch
17:50.43freemangordon*removed
17:51.05freemangordonwe should contact sre
17:51.36Paliyes
17:52.12freemangordonbut first, I will try to have something but green image displayed
18:07.33DocScrutinizer05make sure your video bus switch (actually mux) doesn't operate inverted, enabling front cam when you want main and vice versa
18:09.07DocScrutinizer05check GPIO_97
18:09.18freemangordonDocScrutinizer05: no way, i2c bus is switched there as well
18:09.32freemangordonyes, I do that switching by hand
18:09.34DocScrutinizer05duh! never noticed
18:09.51freemangordonhmm, wait
18:10.00freemangordonit is not i2c bus, my bad
18:10.24freemangordonbut gpio is connected to secondary camera reset
18:10.55freemangordonso if it is not the correct value, secondary camera is held in reset and does not respond to i2c bus red/writes
18:10.58freemangordon*reads
18:11.07DocScrutinizer05o.O
18:11.34freemangordonsee schemati, on page 2
18:11.35DocScrutinizer05indeed, CAM_B_EN
18:11.40freemangordonyeah
18:12.19DocScrutinizer05is this actually reset on front cam module?
18:12.20freemangordonhmm, I get lots of error IRQs
18:12.44freemangordonno, it has another gpio for reset (102)
18:12.48DocScrutinizer05error IRQ?
18:12.54freemangordonyes
18:13.15DocScrutinizer05please elaborate
18:13.33freemangordonsee CSI1B_IRQSTATUS in TRM
18:13.43freemangordonI get 0x615 here :D
18:13.45DocScrutinizer05aah ok
18:14.01DocScrutinizer05you got a pagenumber of TRM for me?
18:14.33freemangordonsure
18:14.45freemangordon1538
18:14.56freemangordonTable 12-138.
18:15.24DocScrutinizer05SPRS599D  ?
18:15.51freemangordonOMAP34xx_ES3.1.x_PUBLIC_TRM_vZM.pdf
18:18.14DocScrutinizer05so SPRUF98?
18:19.19freemangordonDocScrutinizer05: http://46.249.74.23/TRM/
18:19.27DocScrutinizer05ohmy
18:20.03freemangordonDocScrutinizer05: SWPU223M
18:24.45DocScrutinizer05thanks! :-)
18:26.20DocScrutinizer05"bit NNN value 0x0" ??? 0x ?
18:26.45freemangordonhmm?
18:27.07DocScrutinizer05a bit weird to give a hex value for a one bit var
18:27.08freemangordonDocScrutinizer05: elaborate, please
18:27.15freemangordonone bit?
18:27.26freemangordonDocScrutinizer05: CSI1B_IRQSTATUS
18:28.19DocScrutinizer05http://wstaw.org/m/2016/04/15/plasma-desktopug2219.png
18:28.40freemangordonaah
18:28.43freemangordonwell
18:28.52DocScrutinizer05minor but puzzling
18:29.16freemangordonactually not, as this is *field* value
18:29.23DocScrutinizer05you got 0x615?
18:29.29freemangordonit might be longer than 1 bit
18:29.44DocScrutinizer05yes
18:30.15freemangordonthe first is e11, then 411, then 615, which repeats countless times
18:30.36freemangordon615 is the one that repeats
18:30.53DocScrutinizer050b11000010101
18:30.57freemangordonso, yeah
18:31.21freemangordon111000010001
18:31.27freemangordone11
18:32.08freemangordonthat bit 4 (reserved) is actually CRC error
18:32.14freemangordonaccording to the kernel code
18:32.20DocScrutinizer05mhm
18:33.14freemangordonhmm, KP explicitly sets crc to 0
18:34.14DocScrutinizer05according to TRM you write 1(!) to it to reset
18:34.26DocScrutinizer05sounds weird
18:34.28freemangordonso?
18:35.05DocScrutinizer050x0: READS: Event is false. WRITES: Status bit unchanged.        0x1: READS: Event is true (pending). WRITES: Status bit is reset.
18:36.08DocScrutinizer05actually e11 doesn't look like too much of an error, most are just sync notifications
18:36.25DocScrutinizer05just that CRC bit 4
18:36.38DocScrutinizer05aiui
18:37.11DocScrutinizer05and SSC_IRQ bit 0
18:37.22DocScrutinizer05which means it's not synced yet
18:37.35DocScrutinizer05again aiui
18:38.26freemangordonok, CRC disabled, bit 4 is down
18:38.30freemangordonstill no image
18:38.48freemangordonDocScrutinizer05: those sync errors mean that no image will appear
18:39.34DocScrutinizer05I seem to recall you need to write a sync byte (word?)  to cam sensor's "upper left pixel"
18:39.59freemangordonDocScrutinizer05: never heard of that
18:40.03DocScrutinizer05cloudy memories
18:40.27DocScrutinizer05maybe it's hardwired in sensor
18:47.33DocScrutinizer05hmm, sort of there it is: >> Each frame is clearly identified by four unique 32-bit synchronization codes: frame start, frame end, line start, and line end, which are embedded in the serial bitstream. The logical channel identification number is also encoded in the synchronization codes.<<  p1324
18:48.30DocScrutinizer05table 12-8 Sync codes
18:49.03freemangordonDocScrutinizer05: those codes are the same in stock kernel
18:49.08freemangordonalready checked
18:49.14DocScrutinizer05:nod:
18:49.18freemangordon3210
18:49.59DocScrutinizer05sorry, afk. Prolly I'm not much of a help anyway
18:53.06DocScrutinizer05Figure 12-57. CSI1 Receiver Block Diagram    - first thing after CSI input is "Extract SYNC"
18:53.38freemangordonyep, but this is CSI1 that gives errors
18:53.45freemangordonso nothing gets out
18:54.36DocScrutinizer05yes, it seems it doesn't sync
18:55.11DocScrutinizer05on a very low layer
18:55.18freemangordon:nod:
18:55.26DocScrutinizer05bbl
18:55.44freemangordonhowever, this is still HUGE success, so far we've never got ISP interrupts
18:55.55freemangordon*get
18:57.05DocScrutinizer05check module config
18:57.31DocScrutinizer05(huge success) :-)
18:58.41DocScrutinizer05wait, I got some bookmark to some useful contribution regarding camera, from a dunno Jolla devel or sth?
18:58.49DocScrutinizer05I'll try to find that later
18:59.13freemangordonok
18:59.14DocScrutinizer05aah
18:59.21DocScrutinizer05~fptf
18:59.21infobotextra, extra, read all about it, fptf is the Fremantle Porting Task Force, see http://talk.maemo.org/showthread.php?t=91308
19:00.06DocScrutinizer05About camera (about meego/sailfish, but for stuff like zerocopy and omap3camd and how stuff works it applies to fremantle as well, more or less): http://talk.maemo.org/showthread.php...55#post1397155
19:01.17DocScrutinizer05hmm, prolly irrelevant here, not kernel related
19:01.46DocScrutinizer05or is it? omap3camd?
19:04.00DocScrutinizer05anyway, afk for good now
19:04.32freemangordonYEEEAAH
19:05.08freemangordongot frames in mplayer!!!
19:06.11freemangordonPali: ^^^ :)
19:06.18Sicelo\m/
19:06.58Paliwau!!
19:11.02freemangordonwell, there still no video, but no green only as well, I guess I need to tweak brightness etc
19:13.55freemangordonwaw, test patterns seem to work :)
19:13.58freemangordon*wow
19:18.24Sicelowhat test patterns? :)
19:20.25freemangordonvertical strips
19:20.30freemangordoncolor bars
19:20.46freemangordon<PROTECTED>
19:20.46freemangordon<PROTECTED>
19:20.46freemangordon<PROTECTED>
19:20.46freemangordon<PROTECTED>
19:20.46freemangordon<PROTECTED>
19:21.45DocScrutinizer05:-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/ :-D \o/
19:22.10DocScrutinizer05amazing what a lil bit of syncing can do, eh? ;-)
19:22.57freemangordonwell, those bars are heavily distorted, I see way more than 8, an they are almost horizontal
19:22.59DocScrutinizer05wait, who generates the test patterns? cam module or CSI interface in SoC?
19:23.00freemangordonbut this ia a matter of tweaking
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19:23.09freemangordonI guess it is cam module
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19:24.01DocScrutinizer05(distorted) sounds like wrong resolution
19:24.20freemangordonrather wrong pixel rate
19:24.31DocScrutinizer05aka dividers for DMA addressing
19:24.48freemangordonwell, there are at least 10 dividers :D
19:25.00DocScrutinizer05pixel rate is sort of fixed, err synced. CSI has a clock and data differential line
19:25.13freemangordonno, it is not
19:25.33freemangordoncamera module gets external clock and has its own pll
19:25.47DocScrutinizer05it's not fixed, it's controlled by cam module aiui, and the CSI IF is synced to that
19:25.54DocScrutinizer05aah ok
19:26.05DocScrutinizer05then the cam PLL can be off too
19:26.44freemangordonloks like, as it reports `Pixel Rate' min 0 max 0 step 0 default 0 current 12000000.
19:27.45freemangordonhmm, this might be ok
19:28.05DocScrutinizer05anyway you got (at least) one modulo divider for horizontal and one for vertical addressing in DMA on SOC, and you get a resolution setting that prolly works similar in cam module, both must match or the wrong pixel data will end on the wrong RAM address
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19:29.02freemangordonthe pipeline is way more complicated, you have CSI then CCDC then previewer then resizer :)
19:29.37DocScrutinizer05sync between the two modulo divider groups gets done by CSI clk and table 12-8 Sync codes
19:30.03DocScrutinizer05yeah sure there is more complicated stuff in it than just taht
19:30.27DocScrutinizer05particularly resizing is 'fun' to get right, I guess
19:31.12freemangordonanyway, I think I did enough for today, will wait for sailus to appear to give some hints on where to look at
19:36.02DocScrutinizer05good job, you earned your glass of spirit of your choice ;-D
19:36.17freemangordon:)
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