06:00.34 | *** join/#elinux vstehle (~vstehle@88.121.149.49) |
10:55.09 | *** join/#elinux Ododo (~olivier@unaffiliated/ododo) |
15:29.45 | *** join/#elinux alan_o (~alan@99-117-187-177.lightspeed.dybhfl.sbcglobal.net) |
16:03.32 | *** join/#elinux m4t (~matt@shenzhen.guangdong.systems) |
19:07.29 | *** join/#elinux ptesarik (~tesarik@2a00:1028:83b8:1e7a:e22d:a8f9:80f8:b0a7) |
20:43.38 | *** join/#elinux m4t (~matt@shenzhen.guangdong.systems) |
21:31.10 | *** join/#elinux ptesarik (~tesarik@2a00:1028:83b8:1e7a:5a6e:d5af:320a:e57) |
21:51.30 | *** join/#elinux vstehle (~vstehle@88.121.149.49) |
23:49.20 | *** join/#elinux jaakkos (~jaakkos@unaffiliated/jaakkos) |
23:49.54 | jaakkos | Hi all! I'm wondering, in sequential write to DRAM on Cortex A9, what kind of performance hit is expected when CPU caches are disabled? |
23:50.05 | jaakkos | On my Zynq 7045 system, excluding some RAM in device tree and using that via mmap() from /dev/mem, I'm seeing only 120 MB/s sequential write speed, while malloc()+mlock() write speed is 2 GB/s |
23:50.18 | jaakkos | Using this (mmap()) https://paste.debian.net/plainh/2417936c vs. (malloc()) https://paste.debian.net/plainh/b9f6a70e |
23:50.29 | jaakkos | I would like to understand a bit why the performance behaves like this. Is it due to lack of write combining from L1/L2 caches? |