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| 23:49.54 | jaakkos | Hi all! I'm wondering, in sequential write to DRAM on Cortex A9, what kind of performance hit is expected when CPU caches are disabled? |
| 23:50.05 | jaakkos | On my Zynq 7045 system, excluding some RAM in device tree and using that via mmap() from /dev/mem, I'm seeing only 120 MB/s sequential write speed, while malloc()+mlock() write speed is 2 GB/s |
| 23:50.18 | jaakkos | Using this (mmap()) https://paste.debian.net/plainh/2417936c vs. (malloc()) https://paste.debian.net/plainh/b9f6a70e |
| 23:50.29 | jaakkos | I would like to understand a bit why the performance behaves like this. Is it due to lack of write combining from L1/L2 caches? |